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75V16F64GS16
ISSI
PRELIMINARY INFORMATION AUGUST 2002
(R)
64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP)
MCP FEATURES * Power supply voltage of 2.7 to 3.1 volt * High performance: - Flash access time as fast as 70 ns
- PSRAM access time as fast as 80 ns
* WP/ACC Input Pin
- At VIL, allows protection of "outermost" 2 x 8 Kbytes on both ends of boot sectors, regardless of sector protection/unprotection status - At VIH, allows removal of boot sector protection - At VACC, program time will be reduced by 40 %
* Package: 65-Ball FBGA * Operating Temperature: -30C to +85C FLASH MEMORY FEATURES * 0.16 m Process Technology * Simultaneous Read/Write Operations (Dual Bank) * FlexBankTM architecture
- Bank A : 8 Mbit ( 8 KB x 8 and 64 KB x 15) - Bank B : 24 Mbit (64 KB x 48) - Bank C : 24 Mbit (64 KB x 48) - Bank D : 8 Mbit ( 8 KB x 8 and 64 KB x 15) - Two virtual Banks are chosen from the combination of four physical banks (Refer to "Example of Virtual Banks Combination Table" and Simultaneous Operation Table" in FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY) - Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. - Read-while-erase - Read-while-program Single 3.0 V Read, Program, and Erase - Minimized system level power requirements Minimum 100,000 Program/Erase Cycles Sector Erase Architecture - Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word - Any combination of sectors can be concurrently erased - Supports full chip erase Hidden ROM (Hi-ROM) Region - 256 byte of Hi-ROM, accessible through a new "HIROM Enable" command sequence - Factory serialized and protected to provide a secure electronic serial number (ESN)
* Embedded EraseTM Algorithms * * * * * * *
- Automatically preprograms and erases the chip or any sector Embedded ProgramTM Algorithms - Automatically writes and verifies data at specified address Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion Ready/Busy Output (RY/BY) - Hardware method for detection of program or erase cycle completion Automatic Sleep Mode - When addresses remain stable, the device automatically switches itself to low power mode. Low VCCf Write Inhibit 2.5 V Program Suspend/Resume - Suspends the program operation to allow a read in another byte Erase Suspend/Resume - Suspends the erase operation to allow a read data and/or program in another sector within the same device
* * *
PSRAM FEATURES * Power Dissipation:
- Operating : 20 mA Max - Standby : 70 A Max - Power Down : 10 A Max Power down Control by CE2r Byte Write Control : LB (DQ7-DQ0), UB (DQ15-DQ8) 4 words Address Access Capability
*
* * *
Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
1
75V16F64GS16
ISSI
C D E F G H J K
(R)
PIN CONFIGURATION (64 Mb Flash and 16 Mb PSRAM) PACKAGE CODE: D 65 BALL FBGA (Top View) (9.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch)
A
B
10
NC NC
9
NC A15 A21 NC A16 Vccf GND NC
8
A11 A12 A13 A14 NC DQ15 DQ7 DQ14
7
A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5
6
WE CE2r A20 DQ4 Vccr NC
5
WP/ACC RESET RY/BY DQ3 Vccf DQ11
4
LB UB A18 A17 DQ1 DQ9 OE CEf DQ10 DQ2
3
A7 A6 A5 A4 GND DQ0 CE1r DQ8
Common Flash Only
NC A3 A2 A1 A0 NC
2 1
NC NC NC
PSRAM Only
PIN DESCRIPTIONS
A0-A19 A20-A21 RESET RY/BY CEf OE WE Address Inputs, Common Address Inputs, Flash LB UB WP/ACC RY/BY NC Vccf GND Vccr
Lower-byte Control, PSRAM Upper-byte Control, PSRAM
DQ0-DQ15 Data Inputs/Outputs, Common
Hardware Reset Pin/Acceleration, Flash
Write Protect/Acceleration, Flash Ready/Busy Output No Internal Connection Device Power Supply, Flash Device Ground, Common Device Power, PSRAM
CE1r,CE2r Chip Enable, PSRAM
Ready/Busy Output, Flash Open Drain Output
Chip Enable, Flash Output Enable, Common Write Enable, Common
2
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
MCP BLOCK DIAGRAM
Vccf GND A21-A0 A21-A0 RY/BY
ISSI
(R)
WP/ACC RESET CEf
64-MBIT Flash Memory DQ15-DQ0
VCCr GND A19-A0 LB UB WE OE CE1r CE2r DQ15-DQ0 16-MBIT Static PSRAM
DQ15-DQ0
LOGIC SYMBOL
22 A21-A0 CEf CE1r CE2r OE WE WP/ACC DQ15-DQ0 RESET UB LB x16 RY/BY
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
3
75V16F64GS16
FLASH MEMORY BLOCK DIAGRAM
ISSI
OE
(R)
VCC
A21-A0
Upper Bank Address
Y-Decoder
Upper Bank
Latches and Control Logic
DQ15-DQ0
GND
A21-A0 RESET WE CE WP/ACC DQ15-DQ0
A21-A0 X-Decoder STATE CONTROL & COMMAND REGISTER
Status Control
DQ15-DQ0
X-Decoder A21-A0 DQ15-DQ0 A21-A0 Lower Bank Address
Lower Bank
OE
4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
Latches and Control Logic
Y-Decoder
75V16F64GS16
DEVICE BUS OPERATIONS
OPERATION(1,2) Full Standby Output Disable(3) Read from Flash(4) Write to Flash Read from PSRAM(5) Write to PSRAM
CEf CE1r CE CE1 CE2r OE WE LBs LB UBs UB
ISSI
DQ7-DQ0 DQ15-DQ8 RESET WP WP/ACC(7)
(R)
H H L L L H H
H L H H H L L
H X X X X H H
X H H L H L H
X H H H L H L
X X X X X X L H L X X
X X X X X X L L H X X
High-Z High-Z High-Z DOUT DIN DOUT DIN High-Z DIN X High-Z
High-Z High-Z High-Z DOUT DIN DOUT DIN DIN High-Z X High-Z
H H H H H H H
X X X X X X X
Temporary Sector Group Unprotection(6) Flash Hardware Reset Boot Block Sector Write Protection PSRAM Power Down(8)
X X
X H
X H
X X
X X
VID L
X X
X X
X X
X L
X X
X X
X X
X X
X X
X X
X X
L X
Legend : L = VIL, H = VIH, X = VIL or VIH. See "DC CHARACTERISTICS" for voltage levels. Notes:
1. Other operations not indicated in this table are prohibited. 2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once. 3. PSRAM Output Disable condition should not be kept longer than 1 ms. 4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 5. PSRAM Byte control at Read operation is not supported. 6. Also used for the extended sector group protections. 7. Protects "outermost" 2 8 Kbytes (4 words) on both ends of the boot block sectors. 8. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
5
75V16F64GS16
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY
Bank Type
BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankA BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB
ISSI
Bank Type
BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankB BankC 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h
(R)
Sector Address K-Word Address
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35
Sector Address K-Word Address
SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 200000h
6
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY (Continued)
Bank Type
BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC
ISSI
Bank Type
BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankC BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD BankD 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h
(R)
Sector Address K-Word Address
SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106
Sector Address K-Word Address
SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
7
75V16F64GS16
FLEXBANK TM ARCHITECTURE TABLE Bank 1
Bank Split 1 2 3 4 Volume 8 Mbit 24 Mbit 24 Mbit 8 Mbit Combination Bank A Bank B Bank C Bank D Volume 56 Mbit 40 Mbit 40 Mbit 56 Mbit
ISSI
Bank 2
Combination Bank B, C, D Bank A, C, D Bank A, B, D Bank A, B, C
(R)
EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE Bank 1
Bank Split Volume 1 8 Mbit Combination Bank A Sector Size 8x4 Kword 15x32 Kword 2 16 Mbit Bank A,D 16x4 Kword 30x32 Kword 3 24 Mbit Bank B 48x32 Kword 40 Mbit Bank A, C, D 16x4 Kword 78x32 Kword 4 Notes:
1) When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, if erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out. They would output the sequence flag once they were selected. Meanwhile the system would get to read from either Bank C or Bank D.
Bank 2
Volume 56 Mbit Combination Bank B, C, D Sector Size 8x4 Kword 111x32 Kword 48 Mbit Bank B,C 96x32 Kword
32 Mbit
Bank A,B
8x4 Kword 63x32 Kword
32 Mbit
Bank C,D
8x4 Kword 63x32 Kword
8
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
SIMULTANEOUS OPERATION TABLE
Case
1 2 3 4 5 6 7 Note:
ISSI
Bank 1 Status
Read Mode Read Mode Read Mode Read Mode Autoselect Mode Program Mode Erase Mode
(1)
(R)
Bank 2 Status
Read Mode Autoselect Mode Program Mode Erase Mode (1) Read Mode Read Mode Read Mode
1) By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. 2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) means to specify each of the Banks.
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
9
75V16F64GS16
SECTOR ADDRESS TABLE
Bank Address Bank
Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B
ISSI
Sector Address Address Range Word Mode
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh
(R)
Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X
10
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
SECTOR ADDRESS TABLE (Continued)
Bank Address Bank
Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B
ISSI
Sector Address Address Range Word Mode
0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh
(R)
Sector
SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
11
75V16F64GS16
SECTOR ADDRESS TABLE (Continued)
Bank Address Bank
Bank B Bank B Bank B Bank B Bank B Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C
ISSI
Sector Address Address Range Word Mode
1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh
(R)
Sector
SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
12
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
SECTOR ADDRESS TABLE (Continued)
Bank Address Bank
Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D
ISSI
Sector Address Address Range Word Mode
2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3F8FFFh 3F9000h to 3F9FFFh 3FA000h to 3FAFFFh 3FB000h to 3FBFFFh 3FC000h to 3FCFFFh 3FD000h to 3FDFFFh 3FE000h to 3FEFFFh 3FF000h to 3FFFFFh
(R)
Sector
SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
13
75V16F64GS16
SECTOR ADDRESS GROUP TABLE Sector
SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32
ISSI
Sectors
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 to SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X
(R)
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
14
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
SECTOR ADDRESS GROUP TABLE (Continued) Sector
SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47
ISSI
Sectors
SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 X X X X X X 0 0 1 1 1 1 1 1 1 1 1 X X X X X X 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X 0 1 0 1 0 1 0 1
(R)
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH MEMORY AUTOSELECT CODES TABLE
Type Manufacture's Code Device Code Extended Device Code
(2)
A21 to A12 BA BA BA BA Sector Group Address
A6 L L L L L
A3 L L H H L
A2 L L H H L
A1 L L H H H
A0 L H L H L
Code (HEX) 04h 227Eh 2202h 2201h 01h(1)
Sector Group Protection Notes:
Legend: L = VIL, H = VIH. See "n DC CHARACTERISTICS" for voltage levels. 1. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. 2. A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. .
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
15
75V16F64GS16
FLASH MEMORY COMMAND DEFINITIONS
Command Sequence
Bus Write Cycle Req'd First Bus Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Fifth Bus Cycle
ISSI
Sixth Bus Cycle
(R)
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Read / Reset
(1)
1
XXXh
F0h
--
--
--
--
--
--
--
--
--
--
Read / Reset (1)
3
555h
AAh
2AAh
55h
555h (BA) 555h
F0h
RA
RD
--
--
--
--
Autoselect
3
555h
AAh
2AAh
55h
90h
--
--
--
--
--
--
Program
4
555h
B0h
2AAh
55h
555h
A0h
PA
PD
--
--
--
--
Program Suspend
1
BA
30h
--
--
--
--
--
--
--
--
--
--
Program Resume
1
BA
AAh
--
--
--
--
--
--
--
--
--
--
Chip Erase
6
555h
AAh
2AAh
55h --
555h
80h
--
555h
AAh -- AAh
2AAh
55h -- 55h
555h
10h
--
--
555h
--
2AAh
Sector Erase
6
555h
B0h
2AAh
55h
555h
80h
SA
30h
Erase Suspend
1
BA
B0h
--
--
--
--
--
--
--
--
--
--
Erase Resume Extended Sector Group Protection
(3)
1
BA
30h 60h
--
--
--
--
--
--
--
--
--
--
4
XXXh
SPA
60h
SPA
40h
SPA
SD
--
--
--
--
Set to Fast Mode (2) Flash Program
(2)
3
555h
AAh
2AAh
55h
555h
20h
--
--
--
--
--
--
2
XXXh
A0h
PA
PD (6) F0H
--
--
--
--
--
--
--
--
-- --
Reset from Flash Mode (2) Query
(4)
2
BA (BA) 55h 555h
90h
XXXh
--
--
--
--
--
--
--
1
98h
--
--
--
--
--
--
--
--
--
Hi-ROM Entry Hi-ROM Program Hi-ROM Exit (5)
3
AAh AAh AAh
2AAh
55h
555h
88h
--
--
--
--
--
--
(5)
4
555h
2AAh 2AAh
55h
555h
(HRBA)
A0h
(HRA) PA
XXXh
PD
--
--
--
--
4
555h
55h
555h
90h
00h
--
--
--
--
Notes: 1. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 2. This command is valid during Fast Mode. 3. This command is valid while RESET = VID 4. The valid address is A6 to A0. 5. This command is valid during Hi-ROM mode. 6. The data "00h" is also acceptable.
16
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
FLASH MEMORY COMMAND DEFINITIONS (Continued)
Notes: Address bits A21 to A11 = X = "H" or "L" for all address commands except or Program Address (PA), Sector Address (SA) , and Bank Address (BA) , and Sector Group Address (SPA) . Bus operations are defined in "DEVICE BUS OPERATIONS". RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A21, A20, A19) RD = Data read from location RA during read operation.
ISSI
(R)
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the Hi-ROM area : 000000h to 00007Fh HRBA = Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL) The system should generate the following address patterns : 555h or 2AAh to addresses A10 to A0 Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Command combinations not described in "Flash Memory Command Definitions" are illegal.
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
17
75V16F64GS16
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Tstg TA VIN VOUT VCCf VCCr VIN VACC Notes: Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins(1,2) Voltage with Respect to Ground All Pins VCCf Supply RESET
(1,3) (1) (1,3) (1,2)
ISSI
Min. -55 -30 -0.3 -0.3 -0.2 -0.2 -0.5 -0.5 Max. +125 +85 VCCf + 0.3 VCCr + 0.3 +3.6 +3.6 +13.0 +10.5 Unit C C V V V V V V
(R)
VCCr Supply
WP/ACC(1,4)
1. Voltage is defined on the basis of GND = GND = 0 V. 2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCr + 1.0 V for periods of up to 5 ns. 3. Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot GND to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCr) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns. 4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied. 5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
Rating Symbol TA VCCf VCCr Note:
Voltage is defined on the basis of GND = GND = 0 V.
Parameter Ambient Temperature VCCf Supply Voltages VCCr Supply Voltages
Min. -30 -2.7 -2.7
Max. +85 +3.1 +3.1
Unit C V V
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
DC CHARACTERISTICS
Symbol ILI ILO ILIT ICC1f Parameter Input Leakage Output Leakage RESET Inputs Leakage Current FLASH Vcc (1) Active Current (Read)
(2)
ISSI
Test Conditions VIN=GND to VCCf, VCCr VOUT=GND to VCCf, VCCr VCCf=VCCf max., RESET = 12.5V CEf=VIL, OE=VIH tCycle = 5Mhz tCycle = 1Mhz Min. -1.0 -1.0 -- -- -- -- -- Typ. -- -- -- -- -- -- -- Max. +1.0 +1.0 35 18 4 35 53 Unit A A A mA mA mA mA
(R)
ICC2f ICC3f
ICC4f
ICC5f
IACC ICC1r
ISB1f
ISB2f
ISB3f
ISBr
ISB1r
ISB2r
FLASH Vcc Active CEf=VIL, Current(Program/Erase) OE=VIH FLASH Vcc Active(5) CEf=VIL, Current OE=VIH (Read-While-Program) FLASH Vcc Active(5) CEf=VIL, Current OE=VIH (Read-While-Erase) FLASH Vcc Active CEf=VIL, Current OE=VIH (Erase-Suspend-Program) WP/ACC Acceleration VCCf = Vcc max, Program Current WP/ACC = VACC max PSRAM Vcc Active VCCr = Vccr max, trc / twc = min Current CE1r=VIL, CE2r=VIH, VIN=VIH or VIL, trc / twc = 1 s IOUT=0 mA FLASH Vcc VCCf = Vccf max, CEf= VCCf + 0.3V, Standby Current RESET = VCCf + 0.3V, WP/ACC = VCCf + 0.3V FLASH Vcc VCCf = Vccf max, RESET= GND + 0.3V, Standby Current WP/ACC = VCCf + 0.3V (RESET) FLASH Vcc(3) VCCf = Vcc max., CEf, = GND + 0.3V, Current RESET = VCCf + 0.3V, (Automatic Sleep Mode) WP/ACC = VCCf + 0.3V, VIN = VCCf + 0.3V OR GND + 0.3V PSRAM Vcc Standby VCCr = Vccr max, CE1r = CE2R = VIN, Current VIN=VIH or VIL, IOUT=0 mA PSRAM Vcc Standby VCCr = Vccr max, CE1r VCCr -0.2V, Current CE2r VCCr -0.2V, VIN 0.2 V or VIN VCCr -0.2V IOUT=0 mA PSRAM Vcc Standby VCCr = Vccr max, CE1r VCCr -0.2V, Current(6) CE2r VCCr -0.2V, VIN Cycle time = tRC min, IOUT = 0 mA
--
--
53
mA
--
--
40
mA
-- -- -- --
-- 15 2.5 1
20 20 3.0 5
mA mA mA A
--
1
5
A
--
1
5
A
--
0.5
1
mA
--
--
70
A
--
--
5
mA
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
19
75V16F64GS16
DC CHARACTERISTICS (Continued)
Symbol Parameter IPDr PSRAM VCC Power Down Current VIL VIH VIH VID Test Conditions VCCr = VCCr max., VIN VCCf - 0.2 V OR VIN 0.2 V CE2r 0.2 V, IOUT = 0 mA Min. -- Max. 10
ISSI
Unit A
(R)
VACC
VOL VOH VOL VOH VLKO Notes:
Input Low Level Input High Level (Flash) Input High Level (PSRAM) Voltage for Autoselect and Sector Protection (RESET)(4) Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration (4) Output Low Level VCCr = VCCr min., VCCS=VCCS min. (PSRAM) IOL = 1.0 mA Output High Level VCCr = VCCr min., VCCS=VCCS min. (PSRAM) IOH = -0.5 mA Output Low Level VCCf = VCCf min., VCCS=VCCS min. (Flash) IOL = 4.0 mA Output High Level VCCf = VCCf min., VCCS=VCCS min. (Flash) IOH = -0.1 mA Flash Low Vccf Lock-Out Voltage
-0.3 2.0 2.2 11.5
0.5 VCCf + 0.3 VCCr + 0.3 12.5
V V V V
8.5
9.5
V
-- 2.2 -- VCCf - 0.4 2.3
0.4 -- 0.45 -- 2.5
V V V V V
1. ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns. 4. Applicable for only VCCf applying. 5. Embedded Algorithm (program or erase) is in progress. (@5 MHz) 6. ISB2 r depends on VIN cycle time. Please refer to "APPENDIX A". .
20
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
AC CHARACTERISTICS - CE TIMING
Parameter CEf Recover Time CEf Hold Time CE1r High to WE Invalid time for Standby Entry Symbol Condition -- -- -- Min Max 0 3 20 -- -- --
ISSI
Unit ns ns ns
(R)
tCCR tCHOLD tCHWX
TIMING DIAGRAM FOR ALTERNATING PSRAM TO FLASH
CEf
tCCR CE1r
tCCR
WE
tCHWX tCCR tCHOLD tCCR
CE2r
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
21
75V16F64GS16
FLASH READ ONLY OPERATIONS CHARACTERISTICS
JEDEC Symbol Standard Symbol
ISSI
Condition Min Max 70 CEf = VIL, OE = VIL OE = VIL -- -- -- -- -- 0 -- 70 70 30 25 25 -- Unit ns ns ns ns ns ns ns
(R)
Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occures First RESET Pin Low to Read Mode Test Conditions:
Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCCf Timing measurement reference level Input : VCCf/2 Output : VCCf/2
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX
--
tRC tACC tCE tOE tDF tDF tOH tREADY
--
20
s
22
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
FLASH READ CYCLE
tRC Address tACC CEf
Address Stable
ISSI
(R)
tOE OE
tDF
tOEH
WE
High-Z
tCE
High-Z Output valid
DQ
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
23
75V16F64GS16
FLASH HARDWARE RESET / READ OPERATION TIMING DIAGRAM
ISSI
tRC
(R)
Address
Address Stable
tACC CEf tRH
tRP
tRH
tCE
RESET
tOH
High-Z Output valid
DQ
24
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
WRITE/ERASE/PROGRAM OPERATIONS
JEDEC Symbol tAVAV tAVWL Standard Symbol tWC tAS tASO tAH tAHT tDS tDH tOEH tOEH tCEPH tOEPH tGHWL tGHEL tWS tCS tWH tCH tWPH tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP
ISSI
Min 70 0 12 45 0 30 0 0 10 20 20 0 0 0 0 0 0 35 35 25 25 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns s s
(R)
Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Output Enable Hold Time Toggle and Data Polling CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CE) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CE Setup Time (WE to CE) WE Hold Time (CE to WE) CE Hold Time (WE to CE) Write Pulse Width CEf Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Sector Erase Operation VCC Setup Time Rise Time to VID (2) Rise Time to VID
(3) (1)
--
tWLAX
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
10 0.2
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--
tDVWH tWHDX
-- -- -- --
tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2
-- --
50 500 500 4 100
Voltage Transition Time (2) Write Pulse width (2)
-- -- -- -- --
-- -- -- -- --
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
25
75V16F64GS16
WRITE/ERASE/PROGRAM OPERATIONS (Continued)
JEDEC Symbol
(2)
ISSI
Standard Symbol tOESP tCSP tRB tRP tRH tBUSY tEOE tTOW tSPD Min 4 4 0 500 200 Typ Max Unit s s ns ns ns ns ns s s
(R)
Parameter OE Setup Time to WE Active CE Setup Time to WE Active (2) Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-Out Time Erase Suspend Transition Time Notes:
1. Does not include preprogramming time. 2. For Sector Group Protection operation. 3. For Accelerated Program operation.
-- -- -- -- -- -- -- -- --
-- --
50
--
-- -- -- -- -- -- -- -- --
-- -- -- -- --
90 70
--
20
26
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
FLASH WRITE CYCLE
(WE CONTROL)
ISSI
Data Polling PA PA
(R)
3rd Bus Cycle
Address
555h
tWC CEf tCS OE tGHWL WE tDS
A0h
tAS
tAH
tRC
tCH
tCE
tWP
tWPH
tWHWH1
tOE
tDH PD
DQ7 Dout
tDF
Dout
tOH
DQ
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence.
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27
75V16F64GS16
FLASH WRITE CYCLE
(CEf CONTROL)
ISSI
3rd Bus Cycle Data Polling PA PA
(R)
Address
555h
tWC WE
tAS
tAH
tWS
tWH
OE tGHEL CEf
tCP
tCPH
tWHWH1
tDS
AOh
tDH PD
DQ7 Dout
DQ
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence.
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75V16F64GS16
FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
ISSI
555h tWC 2AAh tAS tAH 555h 555h 2AAh SA(1)
(R)
Address
CEf
tSC tCH
OE
tGHWL
tWP tWPH
WE
tDS tDH
AAh 55h 30h for Sector Erase
DQ
80h
AAh
55h
10h/ 30h
tVCS
Vccf
Notes: 1. SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
29
75V16F64GS16
FLASH AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
ISSI
(R)
CEf OE
tCH tOEH tOE tDF
WE
Data In
tCE
(1)
DQ
DQ7 tWHWH1 or 2
DQ7 = Valid Data
High - Z
DQ0/DQ6 RY/BY
Data In
DQ0 to DQ6 = Output Flag
DQ0 to DQ6 Valid Data
High - Z
tBUSY
tEOE
Notes: 1. DQ7 = Valid Data (the device has completed the Embedded operation.)
30
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75V16F64GS16
FLASH AC WAVEFORMS FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS
ISSI
(R)
ADDRESS
tAHT tASO tAHT tAS
CEf
tCEPH
WE OE
tDH
Data
tOEH
tOEPH
tOEH
tOE
Toggle Data Toggle Data
(1)
tCE
Toggle Data Toggle Data Output Valid
DQ6/DQ2 RY/BY
tBUSY
Notes: 1. DQ6 stops toggling (the device has completed the Embedded operation).
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31
75V16F64GS16
FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM
ISSI
Read tRC Command tWC BA2 (555h) tAS tAH Read tRC BA1 tACC tCE tAHT Command tWC BA2 (PA) Read tRC BA1 Read tRC BA2 (PA) tAS
(R)
ADDRESS
BA1
CEf
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF Valid Output Valid Input (PD) Valid Output Status
DQ
Valid Output
Valid Input (A0h)
Note: 1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1; BA2: Address of Bank 2.
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
BY FLASH RY/BY TIMING DIAGRAM DURING WRITE/ERASE OPERATIONS
ISSI
(R)
CEf
The rising edge of the last write pulse
WE
Entire programming or erase operations
RY/BY
tBUSY
FLASH RESET, RY/BY TIMING DIAGRAM BY
WE
RESET
tRP RY/BY
tRB
tREADY
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
33
75V16F64GS16
FLASH EXTENDED SECTOR GROUP PROTECTION
ISSI
tVCS
(R)
Vccf
tVLHT RESET tVIDR
SPAX SPAX SPAY
tWC
tWC
Address A6, A3 A2, A0 A1 CEf OE WE
tWP
TIME-OUT
Data
60h
60h
40h
01h
60h
tOE
Notes: 1. SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected, TIME-OUT: Time-Out window = 250 s (Min)
34
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
PSRAM READ OPERATIONS
Parameter Read Cycle Time Chip Enable Access Time
(1,3) (1)
ISSI
Symbol tRC tCE tOE tAA tOH
(2)
(R)
Value Min. Max. 90
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
--
80 45 80
Output Enable Access Time
(1)
Chip Enable Access Time(1,4) Output Data Hold Time CE1r Low to Output Low-Z
-- -- --
5 5 0
tCLZ tOLZ
OE Low to Output Low-Z(2) CE1r High to Output High-Z OE High to Output High-Z
(2) (2)
-- -- --
30 25
tCHZ tOHZ tASC tASO tASO(ABS) tAX
(4)
-- --
-5 45 10
Address Setup Time to CE1r Low(5) Address Setup Time to OE Address Setup Time to OE Address Invalid Time(4) CE1r Low to Address Hold Time OE Low to Address Hold Time
(4,8) (3,6) (7)
-- -- --
5
--
90 45 -5 -5 45 45 20 45 20
tCLAH tOLAH tCHAH tOHAH
CE1r High to Address Hold Time OE High to Address Hold Time CE1r Low to OE Low DelayTime CE1r High Pulse Width OE High Pulse Width(6,8,9) OE High Pulse Width Notes:
(7) (4,6,8,9) (8)
-- -- -- --
1000
tCLOL tOLCH tCP tOP tOP(ABS)
OE Low to CE1r High DelayTime
-- --
1000
--
1. The output load is 30 pF. 2. The output load is 5 pF. 3. The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. 4. Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access. 5. Applicable if OE is brought to Low before CE1r goes Low. 6. The tASO, tCLOL (Min) and top (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) . 7. The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access. 8. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) - tCLOL (actual) or tRC (Min) - tOP (actual) . 9. Maximum value is applicable if CE1r is kept at Low.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
35
75V16F64GS16
PSRAM WRTE OPERATIONS
Parameter Write Cycle Time(1) Address Setup Time
(2)
ISSI
Symbol tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH(ABS) tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCD
(7)
(R)
Value Min. Max. 90 0 45 0 0 0 0 0 -5 0 45 20 -3 -5 60 60 15 15 20 0 20 -- -- -- 1000 1000 -- -- -- -- 1000 1000 -- -- -- -- -- -- 1000 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Address Setup Timev CE1r Write Setup Time CE1r Write Hold Time WE Setup Time WE Hold Time LB adnd UB Setup Time LB adnd UB Hold Time OE Setup Time(3) OE Hold Time OE Hold Time
(3,4) (5)
OE High to CE1r Low Setup Time(6) OE High to Address Hold Time CE1r Write Pulse Width WE Write Pulse Width
(1,8) (1,8)
CE1r Write Recovery Time(1,9) WE Write Recovery Time(1,3,9) Data Setup Time Data Hold Time CE1r High Pulse Width(9) Notes:
1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . 2. New write address is valid from either CE1r or WE that is brought to High. 3. Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High. 4. The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. 5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stay Low. 6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1r Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. 7. Applicable if CE1r stays Low after read operation. 8. tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively. 9. tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively. The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High. In such a case, the tCP (Min) must be satisfied.
36
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
PSRAM POWER DOWN PARAMETER
Parameter CE2r Low Setup Time for Power down Entry CE2r Low Setup Time after Power down Entry CE1r High Hold Time Following CE2r High after Power down Exit CE1r High Setup Time Following CE2r High after Power down Exit Symbol tCSP tC2LP tCHH tCHS Value Min. Max. 10 100 350 10
ISSI
Unit ns ns s ns
(R)
-- -- -- --
PSRAM OTHER TIMING PARAMETERS
Parameter CE1r High to OE Invalid for Standby Entry CE1r High to WE Invalid for Standby Entry(1) CE2r Low Hold Time after Power-up
(2) (3)
Symbol tCHOX tCHWX tC2LH tC2HL tCHH tT
Value Min. Max. 20 20 50 50 350 1
Unit ns ns s s s ns
CE2r High Hold Time after Power-up
(4)
CE1r High Hold Time Following CE2r High after Power-up(2) Input Transition Time
-- -- -- -- --
25
Notes: 1. Unintended data may be written into any address location if tCHWX is not satisfied. 2. Must satisfy tCHH (Min) after tC2LH (Min) . 3. Requires Power Down mode entry and exit after tC2HL. 4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns, it may violate some timing parameters of AC specification.
PSRAM AC TEST CONDITIONS
Parameter Input HIgh Level Input Low Level Input Timing Measurement Level Input Transition Time Symbol VIH VIL VREF tT Conditon VCCr = 2.7V to 3.1V VCCr = 2.7V to 3.1V VCCr = 2.7V to 3.1V Between VIL and VIH Value 2.3 0.4 1.3 5 Unit V V V ns
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
37
75V16F64GS16
PSRAM READ TIMING
(OE Control Access)
tRC Address tRC
ISSI
(R)
Address Valid tCE tOHAH tASO
Address Valid tOHAH
CE1r tCLOL OE tASO DQ (Input) tOLZ tOHZ tOH tOLZ tOHZ tOH tOE tOP tOE
tOLCH
Note: CE2r and WE must be High during read cycle.
Valid Data Input
Valid Data Input
PSRAM READ TIMING
(CE1r Control Access)
tRC Address tASC CE1r tCP tCHZ OE tCHZ tRC
Address Valid tCE tOHAH
tASC
Address Valid tCE tcHAH
tCLZ DQ (Input)
tOH
tCLZ
tOH
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
38
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
PSRAM READ TIMING
(Address Access after OE Control Access)
tRC
ISSI
tRC
(R)
Address (A19-A2)
Address Valid
Address Valid (No change)
Address (A1, A0) tASO CE1r
Address Valid tOLAH tAX tOE tAA
Address Valid
tOHAH
tOHZ
OE
tOLZ DQ (Input)
tOH
tOH
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
PSRAM READ TIMING
(Address Access after CE1r Control Access)
tRC Address (A19-A2) Address Valid
tRC Address Valid (No change)
Address (A1, A0) tASC CE1r
Address Valid tCLAH tAX tAA
Address Valid
tCHAH
tCE OE
tCHZ
tCLZ DQ (Input)
tOH
tOH
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
39
75V16F64GS16
PSRAM WRITE TIMING
(CE1r Control)
tWC
ISSI
(R)
Address tAS
Address Valid tAH tAS
CE1r
tWS
tCW
tWRC tWH tWS
WE tBS UB, LB tBH tBS
tOHCL OE tDS DQ (Input) tDH
Note: CE2r must be High during write cycle.
Valid Data Input
PSRAM WRITE TIMING
(WE Control, Single Write Operation)
tWC Address tOHAH tAS CE1r tCP tOHCL WE tBS tCS tWP tWR
Address Valid tAH tCH tAS
tBH
UB, LB tOES
OE tOHz DQ (Input) Valid Data Input tDS tDH
Note: CE2r must be High during write cycle.
40
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
PSRAM WRITE TIMING
(WE Control, Continuous Write Operation)
tWC Address tOHAH tAS CE1r tOHCL WE tBS tBS tCS tWP tWR Address Valid tAH tAS
ISSI
(R)
tBH
UB, LB tOES
OE tOHz DQ (Input) Valid Data Input tDS tDH
Note: CE2r must be High during write cycle.
PSRAM READ / WRITE TIMING
(CE1r Control)
tWC Address tCHAH CE1r tCP tWH WE tBS UB, LB tOHCL tCLOL tWS tCW tWH tWRC tWS tAS
Write Address tAH tASC
Read Address
tBH
OE tCHZ tOH DQ (Input) Read Data Output Valid Data Input tDS tDH tOLz tOLz
Note: Write address is valid from either CE1r or WE of last falling edge.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
41
75V16F64GS16
PSRAM READ / WRITE TIMING
(CE1r Control)
ISSI
tRC
(R)
Address tWRC tASC
Read Address tAS tCHAH
Write Address
CE1r
tWRC (Min) tWH tWS tWH
tCP tWS
WE tBH UB, LB tOEH tOHCL
tCE
tBS
OE tCHZ tOH DQ Write Data Input Read Data Output tCLz tOH
Note: CE2r must be High during write cycle.
PSRAM READ / WRITE TIMING
(READ = OE Control, WRITE = WE Control)
tWC Address tAS tOHAH CE1r Low tWP WE tBS UB, LB tOES tOEH tBH tWR
Write Address tAH tASO
Read Address
OE tOHZ tOH DQ Read Data Output Write Data Input tDS tDH tOLz
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE.
42
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
PSRAM READ / WRITE TIMING
(READ = OE Control, WRITE = WE Control)
ISSI
tRC
(R)
Address tASO
Read Address tOHAH tAS
Write Address
CE1r
Low tWR
WE tBH tBS
UB, LB tOEH tOE tOES
OE tOHZ tDH DQ Write Data Input Read Data Output tOLZ tOH
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled OE.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
43
75V16F64GS16
PSRAM POWER DOWN TIMING
CE1r tCHS CE2r
ISSI
(R)
tCSP
tC2LP High - Z
tCHH
DQ Power Down Entry Power Down Mode Power Down Exit
PSRAM STANDBY ENTRY TIMING AFTER READ WRITE
CE1r tCHOX OE tCHWX
WE
Active (Read)
Standby
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period from either last address transition of A0 and A1, or CE1r Low to High transition.
44
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
PSRAM POWER UP TIMING 1
ISSI
(R)
CE1r tCHS tC2LH tCHH
CE2r
Vccr 0V
Vccr Min
Note: It is recommended CE2r to be kept at Low during Vccr power-up. The tC2LH specifies after Vccr reaches specified minimum level.
PSRAM POWER UP TIMING 2
CE1r tC2HL
tCSP tC2LP
tCHS tCHH
CE2r tC2HL Vccr Min 0V
Note: The tC2LH specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must be brought to High prior to or together with CE2r Low to High transition.
Vccr
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PRELIMINARY INFORMATION Rev. 00A 08/01/02
45
75V16F64GS16
FLASH ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle Note:
1. Test conditions TA = +25 C, VCC = 2.9V, Data = Checker
ISSI
Min. -- -- -- 100,00 Max. 0.2 6.0 -- -- Typ.(1) 1.0 60 200 -- Unit s s s cycle Remarks Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead
(R)
46
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Vccr Data Retention Supply Voltage Vccr Data Retention Supply Current Conditions CE1r = CE2r VCCr -0.2V OR, CE1r = CE2r = VIH 2.3 V VCCr 2.7 V, VIN = VIH (1) or VIL CE1r = CE2r = VIH (1), IOUT = 0 MA 2.3 V VCCr 2.7 V, VIN 0.2 V or VIN VCCr -2.0 V, CE1r = CE2r VCCr -0.2 V IOUT = 0 MA 2.7 V VCCr 3.1 V, At Data Retention Entry 2.7 V VCCr 3.1 V, After Data Retention -- Min. 2.1 -- Max. 3.1 1
ISSI
Unit V mA
(R)
VDR IDR
IDR1
Vccr Data Retention Supply Current
--
70
A
tDRS tDRR
V/t
Data Retention SetupTime Data Retention RecoveryTime
0 90 0.5
-- -- --
ns ns V/s
VCCR Voltage Transition Time
Note: 1. 2.0 V VIN VCCr + 0.3
PSRAM DATA RETENTION TIMING
tDRS 3.1V 2.7V 2.3V CE2r CE1r 4.0V GND
Data Retention Mode Data bus must be in High-Z at data retention entry
V/t
tDRR
V/t
Vccr
CE1r = CE2r >Vccr - 0.2V or VIH(1) Min
Note:
1. 2.0 V VIH VCCr + 0.3 V
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
47
75V16F64GS16
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol CIN COUT CIN2 CIN3 Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Conditions Min. 11 12 14 21.5 Max. 14 16 16 26
ISSI
Unit pF pF pF pF
(R)
=0V VOUT = 0 V VIN = 0 V VIN = 0 V
VIN
Notes: 1. Test conditions TA = +25 C, f = 1.0 MHz
HANDLING OF PACKAGE:
Please handle this package carefully since the sides of package created with acute angles.
CAUTION:
1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET. 2) Without the high voltage (VID) , sector group protection can be achieved by using "Extended Sector Group Protection" command.
ISB2r VS VIN Cycle Time
ISB2r vs. VIN Cycle Time (VCCr = 3.0 V)
2.5
2.0
ISB2r (mA)
1.5
: RT = 25 C : LT = -30 C : HT = 85 C
1.0 0.5 0.0 0 200 400 600 800 1000
VIN Cycle Time (ns)
48
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
75V16F64GS16
BALL GRID ARRAY - 65-Ball FBGA PACKAGE CODE: D - 9.0 mm x 9.0 mm Body, 0.8 mm Ball Pitch
ISSI
o 0.45 + 0.10/-0.05 (65X)
(R)
ABCDE FGH J K
K J HGF EDCBA
10 9 8 7 6 5 4 3 2 1
e
D D1
10 9 8 7 6 5 4 3 2 1
e E1 E
A1
SEATING PLANE
A
Symbol A A1 D D1 E E1 e
Min. 1.09 0.29 8.90 -- 8.90 -- --
Typ. 1.19 0.39 9.00 7.20 9.00 7.20 0.80
Max. 1.34 0.49 9.10 -- 9.10 -- --
Units mm mm mm mm mm mm mm
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02
49
75V16F64GS16
ORDERING INFORMATION Industrial Range: -30C to +85C
SRAM Data Boot Bus Section 16 PC Flash Bank Organization PC Flash PSRAM Speed(ns) Speed(ns) 70 80
ISSI
(R)
Order Part No. IS75V16F64GS16-7080DI
Package 65-ball FBGA
50
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 08/01/02

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